We’re excited to launch LLZK, an open-source intermediate representation (IR) for zero-knowledge circuits. Think LLVM, but for ZK. Built by @VeridiseInc and supported with a grant from the @ethereumfndn, LLZK is now live on GitHub. Thread 🧵 1/4

When we started working on ZK tooling, there was nothing available. @FormallyJon shares our zero-knowledge tooling journey at @HouseofZK interview.

What led us to develop Vanguard, our static analyzer, and how did we extend it beyond Solidity? @FormallyJon explains on the @HouseofZK podcast.

Cannes, you were amazing! Thanks to everyone who stopped by our booth, and to @EthCC for hosting us. Here’s a visual feast from the week 🌞

Greetings from @EthCC — Our CTO @KFerles is sharing how we deliver lasting determinism for zkVMs such as @RiscZero

Get an overview of Veridise’s ZK tools and a glimpse into what’s next. @IsilDillig shares our future directions at the @a16zcrypto event.

Our ZK detection tools previously timed out on 30% of ZK circuits. How did we solve this? @IsilDillig shares insights from our recent research paper.

How do we keep ZK circuits rock-solid and deterministic during audits? Our co-founder @IsilDillig shares insights on combining static analysis and SMT solvers in our ZK tools.

Are over-constrained circuits a challenge in zero-knowledge circuits? Which poses a bigger threat: under-constrained or over-constrained circuits? @IsilDillig breaks it down.

Last but not least, the SIGPLAN Robin Milner Young Researcher Award was also announced at PLDI. This year, the award went to Işıl Dillig (@IsilDillig), whose research has had profound and far-reaching contributions to program analysis, verification, and synthesis ⭐️